Grinding technique for integrated circuits

Details Grinding technique for integrated circuits Grinding technique for integrated circuits

1997-02-04

2000-10-03

Niebling, John F.

Semiconductor device manufacturing: process

Semiconductor substrate dicing

438462, 438974, H01L 21301, H01L 2146, H01L 2178

Patent

active

061272450

ABSTRACT:
An integrated circuit die and method of fabricating the same. The method comprises further grinding, polishing or otherwise treating one or more perimeter edges of an individual circuit die. The perimeter edges are treated to remove a substantial portion of the remaining substrate material layer or scribe therefrom without exposing the active circuitry of the die. The process reduces the overall length and width dimensions of a die producing a smaller circuit die without reducing the amount of circuitry on the die.

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Sze, S.M. "Semiconductor Devices Physics and Technology," Wiley & Sons, New York, pp. 314-316, 1985.

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