Method and apparatus for a dynamic, multi-speed bus architecture

Details Method and apparatus for a dynamic, multi-speed bus architecture Method and apparatus for a dynamic, multi-speed bus architecture

1993-03-18

1996-09-24

Sheikh, Ayaz R.

Boots, shoes, and leggings

395306, 395849, 364DIG1, 364240, 3642408, G06F 1300

Patent

active

055599672

ABSTRACT:
In a computer bus arrangement in which a plurality of nodes are interconnected by communication links, control signals are exchanged between the nodes concerning the transmission rate of a data message to be transmitted and the reception rate capability of the nodes. The data message is passed to those nodes which have a reception rate capability which matches or exceeds the transmission rate associated with the message. The other nodes receive a mock data message at a rate within their capability. In order to aid in synchronization within the bus arrangement, the duration of the mock data message is the same as the data message received by the other nodes, even though they are transmitted at different rates.

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