Method of forming a gate overlap LDD structure

Details Method of forming a gate overlap LDD structure Method of forming a gate overlap LDD structure

1993-06-02

1994-04-19

Thomas, Tom

Fishing, trapping, and vermin destroying

437 29, 437192, 437193, 437245, 437913, H01L 21265

Patent

active

053045041

ABSTRACT:
A method is provided for forming a gate overlap LDD structure of an integrated circuit, and an integrated circuit formed according to the same. An oxide layer is formed over a substrate. A four layered gate electrode is formed in an inverse T shape. A first polysilicon layer is formed over the underlying oxide layer. A first conductive layer is formed over the first polysilicon layer. A second polysilicon layer is formed over the first conductive layer. A second conductive layer is then formed over the second polysilicon layer. The second conductive and polysilicon layers are etched to expose a portion of the underlying first conductive layer. Lightly doped drain regions are formed in the substrate adjacent to the second conductive and polysilicon layers. Sidewall oxide spacers are formed on the sides of the second conductive and polysilicon layers and on top of the first conductive layer. The first conductive and polysilicon layers are etched exposing a portion of the underlying oxide layer. Source/drain regions are formed in the substrate adjacent to the first conductive and polysilicon layers.

REFERENCES:
patent: 4935380 (1990-06-01), Okumura
patent: 4997785 (1991-03-01), Pfiester
patent: 5015599 (1991-05-01), Verhaar
patent: 5032535 (1991-07-01), Kamijo et al.
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patent: 5061647 (1991-10-01), Roth et al.
patent: 5102815 (1992-04-01), Sanchez
patent: 5158903 (1992-10-01), Hori et al.
patent: 5162884 (1992-11-01), Liou et al.

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