Circuit forming output pulse a selected delay after initiating p

Details Circuit forming output pulse a selected delay after initiating p Circuit forming output pulse a selected delay after initiating p

1992-01-02

1993-06-08

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307590, 307597, 307601, 307602, 307603, 307605, 328 55, H03K 3017, H03K 5159

Patent

active

052182371

ABSTRACT:
A circuit forms a narrow output pulse by charging a first and a second node during the relatively long interval between output pulses. When an initiating pulse is received, both nodes are discharged rapidly. An inverting amplifier which forms the circuit output has its input connected to the second node, and it produces the output pulse as the complement of the voltage level at this node. Time delay elements establish the width of the output pulse. Just before the time for the fall of the output pulse, the first and second nodes are isolated and the second node is then charged to a voltage to turn off the inverting amplifier and drop the output pulse. The initiating pulse is applied to the discharging circuit through a selected one of two paths that have different delays. The circuit is useful in the support circuits for an FET memory of the type that requires a narrow pulse, Row Address Interlock, following an initiating pulse Row Address Set by a short delay in normal memory operations and by a longer delay in memory refresh operation.

REFERENCES:
patent: 4675546 (1987-07-01), Shaw
patent: 4767947 (1988-08-01), Shah
patent: 4785262 (1988-11-01), Ryu et al.
patent: 4797573 (1989-01-01), Ishimoto
patent: 5008563 (1991-04-01), Kenney et al.

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