Conditional clocking of the second latch of a shift register rat

Details Conditional clocking of the second latch of a shift register rat Conditional clocking of the second latch of a shift register rat

1990-02-23

1992-10-20

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 377 78, 377 81, 328 63, 328 72, H03K 1900, H03K 513

Patent

active

051572869

ABSTRACT:
A logic circuit is presented comprising a plurality of registers 30, 39; each register 30 having first register latches 31, 41 for clocking data into the register 30 in response to a first clock signal 37 and second register latches for clocking data out of the register in response to a second clock signal 38, and combinatorial logic comprising address logic 4 for addressing data to a register and first suppression logic 33 for inhibiting the first clock signal input to the register in response to the address logic, wherein the logic circuit further comprises second suppression logic 34, 35 for inhibiting the second clock signal input to the register in collective response to the address logic and the first clock signal.

REFERENCES:
patent: 3555433 (1971-01-01), Croy
patent: 4627085 (1986-12-01), Yuen
patent: 4961013 (1990-10-01), Obermeyer et al.
IBM Technical Disclosure Bulletin, vol. 18, No. 11, Apr. 1976, pp. 3711-3712, N.Y., US; T. J. Blazejewski et al.: "Secondary path requiring only one additional connection".
IBM Technical Disclosure Bulletin, vol. 30, No. 3, Aug. 1987, pp. 1327-1330, Armonk, N.Y., US; "Reading L2 and gated B clock shift register latches using a bring-up tool to scan out the values while perserving machine state".
Proceedings International Test Conference 1984, 1984, pp. 338-347, IEEE, N.Y., US; H. H. Butt et al.: "Impact of mixed-mode self-test on life cycle cost of VLSI based designs".

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