MOS RAM with implant forming peripheral depletion MOSFET channel

Details MOS RAM with implant forming peripheral depletion MOSFET channel MOS RAM with implant forming peripheral depletion MOSFET channel

1978-01-31

1980-01-08

Larkins, William D.

357 23, 357 45, 357 59, 357 89, 357 51, H01L 2704, H01L 2978, H01L 2994

Patent

active

041830407

ABSTRACT:
In a one transistor, one capacitor N-channel polysilicon gate MOSFET RAM, having self-aligned contacts to silicon gates, an N-implant is used to both form bottom electrodes of the capacitors and to form depletion mode FET channels in peripheral circuits. Separate polysilicon layers are used for the gates of enhancement mode FETs and for the capacitor upper electrodes and depletion FET gates.

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 4021789 (1977-05-01), Furman et al.
patent: 4059826 (1977-11-01), Rogers

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