Method for hierarchic logic verification of VLSI circuits

Details Method for hierarchic logic verification of VLSI circuits Method for hierarchic logic verification of VLSI circuits

1995-07-03

1997-09-23

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, 364491, G06F 1750, H01L 2198

Patent

active

056713991

ABSTRACT:
In a method for hierarchic logic verification of VLSI circuits a hierarchic layout circuit (1234') is acquired from the physical layout of the respective VLSI circuit using an extraction program is compared to a hierarchic logic plan circuit (1234) defined by an appertaining logic plan. They are being compared such that both the layout circuit as well as the logic plan circuit are transformed independently of one another into equivalent circuits (1234") having a respectively minimum plurality of terminals for all sub-circuits and non-isomorphic hierarchies are brought into coincidence during the circuit comparison by temporary, partial expanding. The advantage thereby achieved is that no explicit user rules with respect to the method execution are required, and that substantially less memory space and a significantly shorter processing time are required for the implementation of the method than given non-hierarchic methods.

REFERENCES:
patent: 5519628 (1996-05-01), Russell et al.
Meier et al., "PALACE: A Parallel & Hierarchial Layout Analyzer & Circuit Extractor", Euro Des & Test Conf, IEEE 1996, pp. 357-361.
Meier, "Hierarchial Layout Verification for Submicron Designs"; Euro Des & Test Conf, IEEE 1990, pp. 382-386.
Garbers et al., "Finding Clusters in VLSI Circuits", 1990 Int'l Comp. Aided Des Conf, IEEE, pp. 520-523.
Chowdhury et al., "Hierarchical Layout Synthesis of Analogue VLSI Circuits Using an Intelligent Parsing Mech", 1991 IEEE Midwest Symp. Circ & Sys, pp. 835-838.
IEEE 1993 Custom Integrated Circuits Conference, HCNC: High Capacity Netlist Compare, Rahul Razdan, pp. 17.6.1-17.6.5.
27th ACM/IEEE Design Automation Conference, 1990, "Comparing Structurally Different Views of a VLSI Design", Mike Spreitzer, Paper 11.1, pp. 200-206 .

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