Patent
1991-08-30
1997-09-23
Swann, Tod R.
395842, G06F 1328
Patent
active
056713843
ABSTRACT:
A DMA controller is connected to a CPU in a work station. The controller includes a multiple byte memory address register (MAR), and a pointer register connected between the CPU and MAR. The pointer register is responsive to a command from the CPU to give the CPU successive access to the byte positions of the MAR for writing a memory address thereto. The DMA controller may also include a single byte register associated with the pointer register and connected between the CPU and MAR. The CPU writes an address to the MAR one byte at a time via the single byte register. Preferably, the MAR has a capacity of four 8 bit bytes.
REFERENCES:
patent: 4646232 (1987-02-01), Chang et al.
patent: 4744078 (1988-05-01), Kowalcyzk
patent: 4835733 (1989-05-01), Powell
patent: 4949301 (1990-08-01), Joshi et al.
patent: 5003471 (1991-03-01), Gibson
Microprocessors, Intel Corp., 1990, pp. 4-654 to 4-661.
Beusse James H.
Foote Douglas S.
NCR Corporation
Peikari B.
Swann Tod R.
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