Boots – shoes – and leggings
Patent
1992-04-30
1995-02-21
Harvey, Jack B.
Boots, shoes, and leggings
395425, 3642434, 36424341, 364 25, 364253, 3642563, 3642564, 364DIG1, G06F 1203, G06F 1210
Patent
active
053924100
ABSTRACT:
A 1-dimensional history table, which has been named a TLBLAT, is used to predict some or all of the real address bits that correspond to (i.e., translate from) any given virtual page address in order to provisionally access a real address based cache. The selection of a TLBLAT entry from given virtual address is based on certain address bits in the virtual address. The selection of a TLBLAT entry may also be based on the hashing of such virtual address bits together with other information in order to achieve sufficient randomization. At the minimum, each TLBLAT history table entry records the bits (one or more) necessary for prediction of the congruence class in a real address based cache. The set-associativity of the cache may be as low as one (i.e., a direct-mapped cache). More information may be included in each TLBLAT entry in order to facilitate various design considerations and it is possible even to combine a translation lookaside buffer (TLB) function with the TLBLAT function into a single physical table that provides the functions of both.
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J. H. Chang, H. Chao and K. So, "Cache Design of A Sub-Micron CMOS System/370", Proc. 14th Symposium on Computer Architecture, pp. 208-213 (1987).
Drumheller Ronald L.
Harvey Jack B.
International Business Machines - Corporation
Whitfield Michael A.
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