Semiconductor memory device with EEPROM in trench with polysilic

Details Semiconductor memory device with EEPROM in trench with polysilic Semiconductor memory device with EEPROM in trench with polysilic

1993-07-27

1995-02-21

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

365 63, 365 72, 257316, 257384, 257385, 257755, 257756, G11C 1140

Patent

active

053922379

ABSTRACT:
Provided is a semiconductor memory device wherein nonvolatile memory elements are arranged in a matrix configuration, each of the memory elements having a field effect transistor including a floating gate, an interlayer insulating film and a control gate electrode which are stacked on an insulating film covering a semiconductor substrate, and a source region and a drain region which are respectively formed in the semiconductor substrate on both sides of the gate electrode, the floating gate, interlayer insulating film and control gate electrode being formed in a recess provided in the semiconductor substrate. The semiconductor device of such a structure is reduced in size and highly integrated with its high-performance characteristics maintained.

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D. Campbell et al., "Enhanced Polycide Structures," IBM Tech. Discl. Bull., vol. 25 #4, Sep. 1982, pp. 1920-1921.

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