Result normalizer and method of operation

Details Result normalizer and method of operation Result normalizer and method of operation

1993-12-06

1995-02-21

Malzahn, David H.

Boots, shoes, and leggings

364748, G06F 501, G06F 750

Patent

active

053922280

ABSTRACT:
A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.

REFERENCES:
patent: 5187678 (1993-02-01), Hori
patent: 5204825 (1993-04-01), Ng
patent: 5241490 (1993-08-01), Poon
patent: 5317527 (1994-05-01), Britton et al.
patent: 5343413 (1994-08-01), Inoue

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