Decoder circuit for a static random access memory

Details Decoder circuit for a static random access memory Decoder circuit for a static random access memory

1984-09-11

1987-02-17

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 365230, H03K 19094, H03K 19017, G11C 800

Patent

active

046441891

ABSTRACT:
A decoder circuit for a static random access memory cell and which may be integrated in monolithic form using gallium arsenide field effect transistors. The circuit comprises a first logic NOR-gate P.sub.1 having (n+1) inputs on which the n coded memory address signals or their complements are received, and also the chip-enable selection signal SB. The gate P.sub.1 is connected by a load resistor R to a supply voltage V.sub.DD1. A second NOR-gate P.sub.2 receives the same inputs as the gate P.sub.1 and has as its load a transistor T.sub.0 the gate electrode of which receives the output of the gate P.sub.1 and the drain of which is connected to a power supply voltage V.sub.DD2 which is less than V.sub.DD1. The voltage V.sub.DD2 is also the supply voltage for the memory cell, and is set at the clipping value of the gate junctions of the constituent transistors of that cell. The output V.sub.S of the decoder is produced at the drains of the transistors forming the second NOR-gate P.sub.2 which are connected to the source electrode of the load transistor T.sub.0. The inputs of the NOR-gates receive a chip-enable selection signal SB after application of the n coded memory address signals, thereby achieving reduced access time for the memory cell.

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