Fishing – trapping – and vermin destroying
Patent
1995-07-12
1997-09-23
Niebling, John
Fishing, trapping, and vermin destroying
437 34, 437 41, 437 56, 437160, 437911, 148DIG35, 148DIG88, H01L 21265
Patent
active
056703937
ABSTRACT:
An electrical circuit and method combine junction field effect transistors (JFET) and metal oxide semiconductor (MOS) circuits in series between V.sub.DD and ground, with a feedback of output voltage to control current from V.sub.DD to ground. The electrical circuit comprises a complementary metal oxide semiconductor (CMOS) inverter circuit with an input and an output, and a JFET having a gate coupled to the CMOS inverter for feedback to control the JFET. The JFET and CMOS circuitry is formed on a common substrate with the JFET gate junction being formed by implanting impurity dopants through a layer of gate oxide.
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LSI Logic Corporation
Niebling John
Pham Long
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