Method of making combined metal oxide semiconductor and junction

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 34, 437 41, 437 56, 437160, 437911, 148DIG35, 148DIG88, H01L 21265

Patent

active

056703937

ABSTRACT:
An electrical circuit and method combine junction field effect transistors (JFET) and metal oxide semiconductor (MOS) circuits in series between V.sub.DD and ground, with a feedback of output voltage to control current from V.sub.DD to ground. The electrical circuit comprises a complementary metal oxide semiconductor (CMOS) inverter circuit with an input and an output, and a JFET having a gate coupled to the CMOS inverter for feedback to control the JFET. The JFET and CMOS circuitry is formed on a common substrate with the JFET gate junction being formed by implanting impurity dopants through a layer of gate oxide.

REFERENCES:
patent: 3879619 (1975-04-01), Pleshko
patent: 4373253 (1983-02-01), Khadder et al.
patent: 4395812 (1983-08-01), Bergeron et al.
patent: 4403395 (1983-09-01), Curran
patent: 4523111 (1985-06-01), Baliga
patent: 4527325 (1985-07-01), Geipel et al.
patent: 4551909 (1985-11-01), Cogan et al.
patent: 4558508 (1985-12-01), Kinney
patent: 4568842 (1986-02-01), Koike
patent: 4596068 (1986-06-01), Peters, Jr.
patent: 4602419 (1986-07-01), Harrison et al.
patent: 4654548 (1987-03-01), Tanizawa et al.
patent: 4700461 (1987-10-01), Choi et al.
patent: 4786958 (1988-11-01), Bhagat
patent: 4816705 (1989-03-01), Ohba et al.
patent: 4912053 (1990-03-01), Schrantz
patent: 4947064 (1990-08-01), Kim et al.
patent: 5015596 (1991-05-01), Toyoda et al.
patent: 5120669 (1992-06-01), Schrantz
patent: 5132241 (1992-07-01), Su
patent: 5160855 (1992-11-01), Dobberpahl
patent: 5216294 (1993-06-01), Ryu
patent: 5223449 (1993-06-01), Morris et al.
patent: 5252501 (1993-10-01), Moslehi
patent: 5254864 (1993-10-01), Ogawa
patent: 5266849 (1993-11-01), Kitahara et al.
patent: 5296409 (1994-03-01), Merrill et al.
patent: 5313082 (1994-05-01), Eklund
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5428234 (1995-06-01), Sumi
patent: 5496751 (1996-03-01), Wei et al.
VLSI Fabrication Principles, Silicon and Gallium Arsenide, Sorab K. Ghandhi, Rensselaer Polytechnic Institute, John Wiley & Sons, 1983, pp. 392-394.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of making combined metal oxide semiconductor and junction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making combined metal oxide semiconductor and junction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making combined metal oxide semiconductor and junction will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1938438

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.