Method of manufacturing a semiconductor device comprising resist

Details Method of manufacturing a semiconductor device comprising resist Method of manufacturing a semiconductor device comprising resist

1984-12-19

1987-02-17

Hearn, Brian E.

Metal treatment

Compositions

Heat treating

148188, 148DIG35, 148DIG105, 148DIG147, 29571, 29578, 29576B, 29589, H01L 21283

Patent

active

046437770

ABSTRACT:
There is disclosed a method of manufacturing a semiconductor device comprising the steps of forming a polysilicon film on a semiconductor substrate through an oxidation film, forming a mask of a predetermined pattern on the polysilicon film, forming a molybdenum film on the polysilicon film, and silicifying those regions of said molybdenum film not covered by the mask so that a structure of the uncovered molybdenum film regions and those regions of the polysilicon film located under the uncovered molybdenum regions have low resistance, while a region of the molybdenum film covered by the mask has high resistance.

REFERENCES:
patent: 3484308 (1969-12-01), Lesk
patent: 3566518 (1971-03-01), Brown et al.
patent: 3775192 (1973-11-01), Beale
patent: 3777364 (1973-12-01), Schinella et al.
patent: 3909319 (1975-09-01), Fujiwara et al.
patent: 3918149 (1975-11-01), Roberts
patent: 3976512 (1976-08-01), De Nova et al.
patent: 4025364 (1977-05-01), Smith
patent: 4080718 (1978-03-01), Richman
patent: 4080719 (1978-03-01), Wilting
patent: 4141022 (1979-02-01), Sigg et al.
patent: 4173063 (1979-11-01), Knieykamp et al.
patent: 4224733 (1980-09-01), Spadea
patent: 4285761 (1981-08-01), Fatula et al.
patent: 4290187 (1981-09-01), Stein
patent: 4297782 (1981-11-01), Ito
patent: 4362597 (1982-12-01), Fruser et al.
patent: 4376658 (1983-11-01), Sigusch
patent: 4451328 (1984-05-01), Dubois
Kircher et al. "Fabricating a Gate Field-Effect Transistor" in IBM Technical Disclosure Bulletin, vol. 13, No. 3, Aug. 70, pp. 646-648.
JE0017393, Jun. 1978, Japan, Abstract Only.
Howard "Gate for Mos Devices: . . . " IBM Tech Disc Bull, vol. 21, No. 7, Dec. 1978, pp. 2811-2813.
Laibowitz et al. "Fabrication of Using . . . " IBM Tech Dise Bull, vol. 21, No. 12, May 1979 pp. 5051-5052.
Dash et al., "Method to Fabricate Polysilicon or Polycide Buried Contacts . . . " IBM Tech Disc Bull, vol. 24, No. 6, Nov. 1981, pp. 2863-2866.
Choi et al. "Improved Salicide Process . . . " IBM Tech Disc Bull, vol. 27, No. 7B, Dec. 1984, pp. 4402-4404.
Lien et al. "Electrical Properties of Thin Co.sub.2 Si, CoSi, and CoS.sub.2 . . . " J. Elec Mat. vol. 13, No. 1, 1984, pp. 95-105.
Shibata et al., "An Optimally Designed Process for Submicron MOSFETS," IBM, p. 647-650, 1981.
Okabayashi et al., "Low Resistance MOS Technology Using Self-Aligned Refractory-Silicidation," IEDM, pp. 556-559, 1982.

Affiliated with

Also associated with

Rating

Method of manufacturing a semiconductor device comprising resist does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a semiconductor device comprising resist, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device comprising resist will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1937937