Method of making extremely small area PNP lateral transistor by

Details Method of making extremely small area PNP lateral transistor by Method of making extremely small area PNP lateral transistor by

1981-06-25

1984-08-21

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

148 15, 148187, 357 34, 357 91, H01L 2122, H01L 2131

Patent

active

044661789

ABSTRACT:
An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled moats or slotted regions, wherein the slots are utilized to dope the substrate within the active region. The P type substrate is double energy arsenic planted through one surface to establish a N region to a given depth. This surface is oxidized and photoresist masked conventionally to open regions for the slots which are ion milled or ODE etched to a given depth. P+ regions are established by the slots by ion implanting at an angle such that the entire depth of the slot is not doped but rather the doping is confined to a region within the double energy N implanted depth. Drive-in diffusion enlarges the P+ areas for the emitter and collector and oxidation fills the moat insulating regions around the active area.
The oxide is stripped and the N region enhanced to N+ at the surface, with silox being deposited and opened for metal contacts to the N+ region for the base and the emitter and collector regions. The doping profile of the base region provides a potential barrier to minimize the flow of electrons toward the surface because the emitter electrons are channeled through the less heavily doped part of the base region to the collector.

REFERENCES:
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patent: 4264382 (1981-04-01), Anantha et al.
patent: 4269636 (1981-05-01), Rivoli et al.
patent: 4280854 (1981-07-01), Shibata et al.
patent: 4298402 (1981-11-01), Hingarh
patent: 4378630 (1983-04-01), Horng et al.
Brack et al., IBM-TDB, 16 (1974) 3287.

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