Method for fabricating MESFET device using a double LOCOS proces

Details Method for fabricating MESFET device using a double LOCOS proces Method for fabricating MESFET device using a double LOCOS proces

1981-12-28

1984-08-21

Rutledge, L. Dewayne

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, H01L 2126

Patent

active

044661746

ABSTRACT:
MESFET devices are fabricated on a semiconductor substrate using a LOCOS (localized oxidation of silicon) process twice during the fabrication. The first LOCOS process provides device separation with a self-aligned thick-field oxide (SATO). The second LOCOS provides separation of gate and source/drain regions for each device, and self-aligns the gate contact with the channel implant. Devices fabricated by this method exhibit reduced series resistance, and improved metal step coverage.

REFERENCES:
patent: 3913211 (1975-10-01), Seeds
patent: 4202003 (1980-05-01), Darley
patent: 4248688 (1981-02-01), Gartner
patent: 4253229 (1981-03-01), Yeh
patent: 4277882 (1981-07-01), Crossley
patent: 4304042 (1981-12-01), Yeh
patent: 4309224 (1982-01-01), Shibata
patent: 4356040 (1982-10-01), Fu
"Method for Fabricating a Self-Aligned Vertical PNP Transistor", Isaac et al., IBM Technical Disclosure Bulletin, vol. 22, No. 8A, Jan. 1980, pp. 3203-3206.

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