Gate turn-off thyristor

Details Gate turn-off thyristor Gate turn-off thyristor

1985-02-22

1987-12-01

Edlow, Martin H.

357 64, 357 91, H01L 2974, H01L 29167

Patent

active

047107928

ABSTRACT:
A gate turn-off thyristor comprises a semiconductor wafer (8) structured by an N-base layer (8c), a P-base layer (8b) adjacent to one side of the N-base layer (8c), an N-emitter layer 8d adjacent to the other side of the N-base layer (8c), and a plurality of N-emitter regions (8a) formed on the outer surface of the P-base layer (8b) excluding a region serving as a gate region and further comprises a first electrode (9) on the outer surface of the P-emitter layer (8d), second electrodes (5) on the outer surfaces of the N-emitter regions (8a), a gate electrode (4) on the outer surface of the gate region and a lead-out point (7) for the gate electrode, and the above described gate turn-off thyristor is characterized in that the semiconductor wafer (8) includes a plurality of areas (3A and 3B) having different carrier life times and that the life time is the longest in the first area (3A) where the gate lead-out point (7) is positioned, while the life time is shorter in the area (3B) farther from the gate lead-out point (7).

REFERENCES:
patent: 3943549 (1976-03-01), Jaecklin et al.
patent: 3988771 (1976-10-01), Krishna
patent: 4165517 (1979-08-01), Temple et al.
patent: 4187517 (1980-02-01), Platzoder
Gate Turn-Off in p-n-p-n Devices, E. D. Wolley, IEEE Transactions on Electron Devices, vol. 13, No. 7, Jul. 1966, pp. 590-597.

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