Method of passivating a semiconductor wafer

Details Method of passivating a semiconductor wafer Method of passivating a semiconductor wafer

1992-01-23

1993-06-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437231, 156643, H01L 21469

Patent

active

052179265

ABSTRACT:
Disclosed is a method of passivating a semiconductor wafer having an array of substantially parallel conductive metal runners which are predominantly spaced a defined distance apart relative to adjacent runners throughout the array and which have a predominant height throughout the array. The method includes, a) depositing a first layer of a passivation dielectric insulating material atop the wafer to a selected maximum thickness between the metal runners, the selected maximum thickness being less than the defined distance between adjacent metal runners; b) depositing a layer of photoresist atop the wafer to a selected thickness sufficient to cover the first passivation layer elevationally above the metal runners; c) etching the photoresist and first passivation layer to remove dielectric insulating material from above the metal runners and not remove dielectric insulating material from between the metal runners; d) stripping photoresist from the wafer; and e) depositing a second layer of a passivation dielectric insulating material atop the wafer to a selected thickness sufficient to fill all gaps between adjacent metal runners.

REFERENCES:
patent: 4520041 (1985-05-01), Aoyama et al.
patent: 4775550 (1988-10-01), Chu et al.
patent: 4946550 (1990-08-01), Van Laarhoven
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 5077234 (1991-12-01), Scoopo et al.
S. Wolf, Silicon Processing for the VLSI Era, Volz, Lattice Press, Sunset Beach, CA, 1990, pp. 222-229, 233-235.

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