Fishing – trapping – and vermin destroying
Patent
1992-06-09
1993-06-08
Wilczewski, Mary
Fishing, trapping, and vermin destroying
437979, 437984, H01L 21336, H01L 21265, H01L 29784
Patent
active
052179133
ABSTRACT:
A MOS FET comprises a pair of source and drain impurity regions, a gate oxide film and a gate electrode. The source and drain regions have an LDD structure in which high concentration impurity regions and low concentration impurity regions are set off. The gate electrode is formed to extend over the channel region and contains sidewalls overlying the low concentration impurity regions. In addition, portions of the gate oxide film located between the sidewalls of the gate electrode and the respective low concentration impurity regions are formed to have a film thickness larger than that of the portion located between the gate electrode and the channel region. The thick portion of the oxide film underlying the gate sidewalls form a charge storage layer which reduces the resistance of the low impurity concentration region while minimizing the gate capacitance. In another example, conductive sidewall spacers are formed on sidewalls of a gate electrode through an insulating film. The sidewall spacers are connected with source and drain electrode connections or directly with source and drain impurity regions. Hot carriers generated near the drain are taken out from a gate insulating layer through conductive sidewall spacers. Accordingly, increase of the resistance due to trapped hot carriers can be prevented.
REFERENCES:
patent: 4049477 (1977-09-01), Ligon
patent: 4520553 (1985-06-01), Kraft
patent: 4727038 (1988-08-01), Watabe et al.
patent: 4925807 (1990-05-01), Yoshikawa
patent: 4952993 (1990-08-01), Okumura
patent: 4954867 (1990-09-01), Hosaka
patent: 4978628 (1990-12-01), Rosenthal
Paul J. Tsang et al. "Fabrication of High-Performance LDDFET's Oxide Sidewall Sidewall-Spacer Technology," IEEE Transactions on Electron Devices, vol. EL-29, No. 4, Apr. 1982, pp. 590-596.
Ryuichi Izawa et al. "The Impact of Gate-Drain Overlapped LDD (Gold) for Deep Submicron VLSI's", IEEE Central Research Laboratory, Hitachi Ltd., Kokubunju, Tokyo 1895, Japan, 1987, pp. 38-41.
Inuishi masahide
Mitsui Katsuyoshi
Watabe Kiyoto
Mitsubishi Denki & Kabushiki Kaisha
Wilczewski Mary
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