Low power counting circuits

Details Low power counting circuits Low power counting circuits

1973-05-23

1976-08-03

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307214, 307251, 307269, H03K 2302, H03K 1760, H03K 1908, H03K 1940

Patent

active

039731391

ABSTRACT:
A counter stage comprising a static inverter and first and second dynamic inverting means. Each inverting means includes an input, an output, and means for selectively rendering the inverting means operative. The output of the first inverting means is applied to the input of the static inverter, the output of the static inverter is applied to the input of the second inverting means and the output of the second inverting means is fed back to the input of the first inverting means. When one inverting means is rendered operative, the other inverting means is rendered inoperative.

REFERENCES:
patent: 3716723 (1973-02-01), Heuner et al.
patent: 3720841 (1973-03-01), Suzuki
patent: 3737673 (1973-06-01), Suzuki
patent: 3745371 (1973-07-01), Suzuki
patent: 3749937 (1973-07-01), Rogers

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