Semiconductor memory

Static information storage and retrieval – Addressing

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365189, G11C 1300

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active

047317612

ABSTRACT:
A dynamic RAM with static column function comprising a predecoder for predecoding both the row address and the column address to output intermediate signals, a row decoder composed of NOR circuits for selecting one row in response to said intermediate signals, a column decoder composed of NAND circuits for selecting one column in response to said intermediate signals, and a logic inversion circuit for matching the logics for the intermediate signal between the row decoder and the column decoder.

REFERENCES:
patent: 4429374 (1984-01-01), Tanimura
"A 35ns 64K Static Column DRAM", Fumio Baba et al., IEEE Journal of Solid-State Circuits, Digest of Technical Papers, Feb. 1983, pp. 64-65.
Nikkei Electronics, 1983, F. Baba et al., vol. 9-12, pp. 153-174.

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