Method of fabricating integrated circuit structure having CMOS a

Metal working – Method of mechanical manufacture – Assembling or joining

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29571, 29577C, 148 15, 148187, 148DIG82, 357 42, 357 43, 357 91, H01L 2122, H01L 21265

Patent

active

046047905

ABSTRACT:
An improved method is disclosed for isolating active devices in an integrated circuit structure containing both CMOS and bipolar devices to simultaneously form isolation regions to separate CMOS channels from adjacent channels or bipolar devices as well as to separate adjacent bipolar devices from one another. The improved method of isolation also results in the simultaneous formation of a retrograde p-well for the n-channel device. The improved method comprises implanting, into a substrate having field oxide portions previously grown thereon, impurities capable of forming one or more isolation regions, between the active devices, at an energy level sufficiently high to permit penetration of the impurities through the field oxide.

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patent: 4468852 (1984-09-01), Cerofolini
patent: 4484388 (1984-11-01), Iwasaki
patent: 4509991 (1985-04-01), Taur
patent: 4535532 (1985-08-01), Lancaster
Combs IEEE-IEDM (1981) p. 346.

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