Multiplex communications – Wide area network – Packet switching
Patent
1987-06-29
1989-09-26
Paschall, M. H.
Multiplex communications
Wide area network
Packet switching
370 851, H04Q 1104
Patent
active
048706400
ABSTRACT:
The system comprises input modules (Pei) receiving entering packets, output modules (PSi) transmitting outgoing packets, a control memory (M) with double access and divided into routing modules (PTi, PAj), and a resource control module (GR).
It also comprises an input time-division bus (BHDE) to connect timewise input modules (PEi) to routing modules (PTI, PAj) selected in the central memory (M) and an output time-division bus (BHDS) to connect timewise routing modules (PTi, PAj) of the central memory (M) to output modules (PSi). The control module (GR) is bidirectionally connected to the input modules (PEi) and to the central memory (MO through the input time-division bus (BHDE), on one hand, and to the output modules (PSi) and the central memory (M) by the output time-division bus (BHDS), on the other hand.
REFERENCES:
patent: 4354263 (1982-10-01), Bordry et al.
patent: 4596010 (1986-06-01), Beckner et al.
patent: 4603416 (1986-07-01), Servel et al.
patent: 4674082 (1987-06-01), Flanagin et al.
patent: 4720850 (1988-01-01), Oberlander et al.
patent: 4720854 (1988-01-01), Sand
patent: 4730305 (1988-03-01), Acampora et al.
"A High Throughput Packet Switching System", IEEE /47. Conf. on Communications-F. Ishino et al., 1982.
Cheminel Daniel
Coatrieux Jean-Yvon
Thepaut Bernard
L'Etat Francais, rerpresente par le Secretaire d'Etat aux Postes
National d'Etudes and Etablissement Publie de Diffusion dit
Paschall M. H.
Rubin Daniel
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