Video system having a dual-port memory with inhibited random acc

Details Video system having a dual-port memory with inhibited random acc Video system having a dual-port memory with inhibited random acc

1983-12-30

1987-08-25

Williams, Jr., Archie E.

Boots, shoes, and leggings

365189, G11C 700, G11C 1900

Patent

active

046897410

ABSTRACT:
In video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

REFERENCES:
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patent: 4412313 (1983-10-01), Ackland et al.
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patent: 4562435 (1985-12-01), McDonough et al.
D. A. Kummer et al., All--Points Addressable Raster Scan Graphics for Cathode Ray Tube with Dual--Ported Bit Map, IBM Technical Disclosure Bulletin, (vol. 23, No. 8, Jan. 1981), pp. 3553-3555.

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