Multi-level bus access for multiple central processing unit

Details Multi-level bus access for multiple central processing unit Multi-level bus access for multiple central processing unit

1985-06-10

1990-01-30

Shaw, Gareth D.

Boots, shoes, and leggings

3642402, 364229, 3642292, 3642294, G06F 900, G06F 1300

Patent

active

048977845

ABSTRACT:
A system by which a number of central processing units (CPU's) may be used completely independently of one another, and yet by which any CPU within the system may communicate with any other CPU in the system. The implementation of the system requires each CPU to be physically connected only to its own bus and to the bus of one other CPU even if there are many CPU's and buses in the system. This enables each CPU in the system to have access to all of the buses of all of the other CPU's in the system.

REFERENCES:
patent: 4368514 (1983-01-01), Persaud et al.
patent: 4495567 (1985-01-01), Treen
patent: 4590556 (1986-05-01), Berger et al.

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