Boots – shoes – and leggings
Patent
1987-12-30
1991-09-17
Shaw, Gareth D.
Boots, shoes, and leggings
3642318, 364247, 3642471, 3642474, 3642628, 364263, G06F 922
Patent
active
050500732
ABSTRACT:
A microinstruction executing system includes a sequencer for controlling sequential readout of microinstructions from a ROM for storage in a microinstruction register and for subsequent decoding by a decoder. In response to a destination control signal (source side) from the decoder, a general register will transfer data to a destination bus and in response to a destination control signal (destination side) from the decoder, data from the destination bus will be transferred to one of a destination data register or a source data register. In response to a source control signal (source side) from the decoder, the general register will transfer data to a source bus and in response to a source control signal (destination side) from the decoder data from the source bus will be transferred to one of the destination data register or source data register. Further, in response to an operation control signal from the decoder an arithmetic logic unit will perform an appropriate calculation upon data available to it from either the destination data register or source data register with the result of the calculation being transferred to the destination data register by way of the destination data bus. These operations up to a transferal of the calculated result to the destination data register will occur in the first half period of a microinstruction time while during the second half period of the microinstruction time a like transfer of data a succeeding calculation will be effected in accordance with the same control signals.
REFERENCES:
patent: 3651476 (1972-03-01), Metz et al.
patent: 4041462 (1977-08-01), Davis et al.
patent: 4047161 (1977-09-01), Davis
patent: 4103329 (1978-07-01), Davis et al.
patent: 4131943 (1978-12-01), Shiraogawa
patent: 4156927 (1979-05-01), McElroy et al.
patent: 4228498 (1980-10-01), Moshier
patent: 4240137 (1980-12-01), Matsumoto et al.
patent: 4306285 (1981-12-01), Moriya et al.
patent: 4314333 (1982-02-01), Shibayama et al.
patent: 4382279 (1983-05-01), Ugon
patent: 4396979 (1983-08-01), Mor et al.
patent: 4446533 (1984-05-01), Backhouse
patent: 4449184 (1984-05-01), Pohlman et al.
patent: 4541047 (1985-09-01), Wada et al.
patent: 4564920 (1986-01-01), Briggs
patent: 4594655 (1986-06-01), Hao et al.
patent: 4615004 (1986-09-01), Chevillat et al.
patent: 4616313 (1986-10-01), Aoyagi
patent: 4630195 (1986-12-01), Hester et al.
patent: 4631672 (1986-12-01), Sakamoto
patent: 4656578 (1987-04-01), Chilinski et al.
patent: 4739470 (1988-04-01), Wada et al.
ISSCC 81; Session XVI; Fam 16.2: A 16b; "CMOS/NMOS SOS Microprocessor", Jun Iwamura et al.; 2/20/1981.
Toshiba Review; No. 132; pp. 33-36; "16-Bit SOS Microprocessor T88000"; Masamichi Sugai et al.; 1981.
Fagan Matthew C.
Kabushiki Kaisha Toshiba
Shaw Gareth D.
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