Process for making CMOS field-effect transistors

Metal treatment – Compositions – Heat treating

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148187, 148188, 148190, 29571, 29576B, C22B 2126

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active

042772915

ABSTRACT:
Two patches of silicon nitride are formed above spaced-apart regions of an n-type substrate (2) on an overlying oxide layer (8) of small thickness. Arsenic ions are then implanted through the oxide layer in substrate areas not covered by the patches whereupon one patch (10a) and an adjoining portion of the oxide layer are covered by a photoresist mask (14), leaving unprotected the second patch (10b) and an oxide portion adjacent thereto. The wafer is then bombarded with boron ions, first at a relatively low energy level to penetrate the last-mentioned oxide portion and then at a higher energy level with additional penetration of the second patch (10b) to form a p-well (18) bounded by a p+ guard zone (20); the previously implanted arsenic ions in the unbombarded area form an n+ guard zone (22). Next, the wafer is subjected to a heat treatment in an oxidizing atmosphere with resulting deepening of the guard zones and the p-well and with growth of the oxide layer especially in areas not overlain by the patches whose subsequent removal, together with other oxide portions except for a residue forming two insulating gate supports (24a, 24b), exposes source and drain areas of the p-well (18) and of an n-type pedestal (19) separated therefrom by the guard zones (20, 22). A phosphorus-doped oxide layer (28) is then formed above the p-well whereupon the wafer is heated in a boron atmosphere.

REFERENCES:
patent: 3853633 (1974-12-01), Armstrong
patent: 3986896 (1976-10-01), Veno et al.
patent: 4013484 (1977-03-01), Boleky et al.
patent: 4135955 (1979-01-01), Gasner et al.
patent: 4149915 (1979-04-01), Bohg et al.
Lilen, H., Principes et Applications des CI/MOS, Editions Radio, Paris, France, 1972, pp. 54-59.

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