Synchronization circuitry for duplex digital span equipment

Details Synchronization circuitry for duplex digital span equipment Synchronization circuitry for duplex digital span equipment

1986-11-17

1988-06-28

Masinick, Michael A.

Multiplex communications

Wide area network

Packet switching

375106, H04J 306

Patent

active

047544546

ABSTRACT:
This circuit facilitates the synchronization of two copies of digital control units. These digital control units control a number of digital spans. One copy of this circuit is active at any one particular time. This one copy drives all the remaining circuitry of the digital span interface for both copies of the digital control unit. The other copy of this circuit is typically in the ready-standby mode. It is not actively driving the remainder of the circuitry within its own copy. When one copy of the digital control unit is brought on-line, a framing operation must be performed to determine the proper framing bit for both copies. Circuitry in the cross-copy data path monitors an attempt to synchronize the two digital control unit copies. The data which is sent cross-copy is modified so that all data bits are at logic 1, except for a bit which the active copy believes is the proper S-bit or framing bit. In this manner, the standby copy cannot reframe on any bit, except the one which the active copy believes is the proper framing and synchronization bit.

REFERENCES:
patent: 4234956 (1980-11-01), Adderley et al.
patent: 4477895 (1984-10-01), Casper et al.
patent: 4507780 (1985-03-01), Perry
patent: 4531210 (1985-07-01), Perry
patent: 4656645 (1987-04-01), Kaneko
patent: 4680776 (1987-07-01), Ikeuchi et al.

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