Boots – shoes – and leggings
Patent
1985-10-18
1988-06-28
Zache, Raulfe B.
Boots, shoes, and leggings
365222, G06F 1216, G11C 700
Patent
active
047544252
ABSTRACT:
A dynamic RAM memory refresh circuit is used with a microprocessor. In a small telecommunication switching system, a microprocessor shares access to memory with the dynamic RAM refresh circuit. Since circuitry size is of paramount importance, this circuit may be implemented with CMOS gate array technology. Since memory access is shared by the microprocessor and the dynamic RAM refresh circuit, processor through-put is affected. However, due to the speed of the dynamic RAM refresh circuit, the microprocessor real-time through-put is degraded only from 2 to 5 percent. A row of dynamic RAM memory is refreshed during each memory access by the refresh circuit, so that during a 2 millisecond inteval all dynamic RAM memory is refreshed. In addition, the dynamic RAM refresh circuit provides a strapping option to allow operation of the refresh circuit in conjunction with microprocessors of different clock frequency.
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patent: 4158883 (1979-06-01), Kadono et al.
patent: 4249247 (1981-02-01), Patel
patent: 4332008 (1982-05-01), Shima et al.
patent: 4575826 (1986-03-01), Dean
patent: 4628482 (1986-12-01), Tachiuchi et al.
Bogacz Frank J.
GTE Communication Systems Corporation
Munteanu Florin
Zache Raulfe B.
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