Parallel generation of serial cyclic redundancy check

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364300, 364900, G06F 1110

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043120687

ABSTRACT:
A method and apparatus for assuring the accuracy of data received by any device in a computer system from any other device in the same computer system or from another computer system. The existing hardware of a computer system is utilized to generate a cyclic redundant check character each time a unit of data is transmitted. The cyclic redundant check character is concatenated to the right of such data transmitted. Each time that the particular data is received, the check character and the data with which it is associated, is again manipulated in the same manner as in generating the check character. If the data received is the same as the data transmitted, the result of such manipulation is zero.

REFERENCES:
Nicholson, Cyclic Redundancy Check System, IBM Technical Disclosure Bulletin, vol. 19, No. 9, Feb. 1977, pp. 3350-3351.
Dixon, Exclusive-OR Data Manipulation for Cyclic Code Generation, IBM Technical Disclosure Bulletin, vol. 14, No. 3, Aug. 1971, p. 857.
Vasa, Calculating an Error Checking Character in Software, Computer Design, May 1976, pp. 190-191.
Boudreau and Steen, Cyclic Redundancy Checking by Program, Fall Joint Computer Conference, 1971, pp. 9-15.
Hanover and Jaeger, Programmed Cyclic Redundancy Checking, IBM Technical Disclosure Bulletin, vol. 19, No. 8, Jan. 1977, p. 2867.
P. Bushnell, CRCC Calculation by Software, Electronic Engineering, Aug. 1976, vol. 48, No. 582, p. 17.

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