Process for forming poly-sheet pillar transistor DRAM cell

Details Process for forming poly-sheet pillar transistor DRAM cell Process for forming poly-sheet pillar transistor DRAM cell

1991-06-25

1992-10-20

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437228, 437233, 437919, H01L 2170

Patent

active

051569922

ABSTRACT:
A memory cell comprises a semiconductor pillar and an insulator on a sidewall of the pillar. A conductive capacitor of the memory cell comprises a first electrode adjacent the insulator. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region coupled to the first electrode.

REFERENCES:
patent: 4672410 (1987-06-01), Miura et al.
patent: 4786954 (1988-11-01), Morie et al.
patent: 4830978 (1989-05-01), Teng et al.
patent: 4873560 (1989-10-01), Sunami et al.
patent: 5027173 (1991-06-01), Satoh
patent: 5034787 (1991-07-01), Dhong et al.
"A Surrounding Gate Transistor (SGT) Cell for 64/256 Mbit DRAMs," by Sunouchi et al., ULSI Research Center, Japan, 1989 IEEE pp. 23-26.

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