Method of making a trench dram cell

Fishing – trapping – and vermin destroying

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437 38, 437 47, 437 51, 437 60, 437191, 437203, 437233, 437235, 437919, H01L 2170

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active

050495186

ABSTRACT:
A semiconductor memory, particularly, a dynamic RAM, is provided having a two-cell one-contact memory cell connection structure. A connection portion between memory cells in a silicon substrate of a dynamic RAM, wherein each memory cell has one silicon island enclosed by a trench and provided with two transistor cells within said island, is formed by connecting a polysilicon electrode, enclosing the periphery of the silicon island at the inside of the trench and separated at two portions of the periphery of the silicon island, to the source or drain of one of the two transistor cells of the memory cell. The connection of the polysilicon electrode to the source or drain of the transistor cell of each of two adjacent memory cells can be easily achieved through self aligning by using a fine-trench polysilicon burying method or a selective epitaxial method.

REFERENCES:
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patent: 4734384 (1988-03-01), Tsuchiya
patent: 4830978 (1989-03-01), Teng et al.
patent: 4921816 (1990-05-01), Ino
S. Nakajima et al., "An Isolation-Merged Vertical Capacitor Cell Large Capacity Dram", IEDM 84, pp. 240-243.
D. Kenney et al., "16-MBIT Merged Isolation and Node Trench SPT Cell (Mint)", 1988 Symposium on VLSI Technology, pp. 25-26.
T. Kaga et al., "A 5.4 M.sup.2 Sheath-Plate-Capacitor DRAM Cell with Self-Aligned Storage-Node Insulation", 19th Conference on Solid State Devices and Materials, Tokyo, 1987, pp. 15-18.
G. Fuse et al., "SCC (Surrounded Capacitor Cell) Structure for Dram", 19th Conference on Solid State Devices and Materials, Tokyo, 1987, pp. 11-14.

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