Fishing – trapping – and vermin destroying
Patent
1990-01-18
1991-09-17
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437200, 437 45, 437941, 148DIG147, 148DIG19, H01L 21336
Patent
active
050495143
ABSTRACT:
In a method of manufacturing a semiconductor device of polycide gate structure, a polysilicon layer is formed on the gate insulation film. The polysilicon layer and the gate insulation film are selectively removed to form an opening which reaches the semiconductor substrate in the polysilicon layer and the gate insulation film. After this, a silicide film is formed directly on the polysilicon layer and an exposed part of the semiconductor substrate and then ion-implantation is effected to form source and drain regions. According to the manufacturing method, since the silicide film is formed in direct contact with the semiconductor substrate, charges caused by the ion-implantation can be easily discharged into the semiconductor substrate. Therefore, no gate charge will occur. Further, the gate oxide film is prevented from being brought into contact with the masking photoresist layer by the presence of the polysilicon layer. Therefore, damage of the surface of the gate oxide film due to the direct contact with the photoresist layer will not occur and unwanted material may be prevented from being injected from the photoresist layer into the gate oxide film.
REFERENCES:
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patent: 4740479 (1988-04-01), Neppl et al.
patent: 4788160 (1988-11-01), Havemann et al.
patent: 4859278 (1989-08-01), Choi
Murarka, S. P., Silicides for VLSI Applications, Academic Press, TK7871.15.S54M8, 1982, pp. 30-31, 116-119.
Eurpoean Search Report, 90100301.2.
Hearn Brian E.
Kabushiki Kaisha Toshiba
Quach T. N.
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