Scalable receiver structure for efficient bit sequence decoding

Details Scalable receiver structure for efficient bit sequence decoding Scalable receiver structure for efficient bit sequence decoding

1997-06-30

2000-05-30

Pham, Chi H.

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

370514, H04L 700

Patent

active

060699280

ABSTRACT:
Synchronization words, contained within a data transmission are detected by oversampling the incoming data transmission by a factor of M. Each of M samples are stored in a respective register on an ongoing basis and a receiver is activated to monitor the contents of all registers to determine if they contain a synchronization word. Commonly a plurality of registers may detect the presence of a synchronization word simultaneously. The one having the largest amplitude bit samples is selected and the receiver changes mode to monitor the output of that register while another receiver is activated to monitor all registers. This is particularly useful in detecting synchronization words or flags in data packets, particularly in modem to modem communications.

REFERENCES:
patent: 5371737 (1994-12-01), Nelson et al.
patent: 5373536 (1994-12-01), Dehner, Jr. et al.
patent: 5638054 (1997-06-01), Davis et al.
patent: 5701329 (1997-12-01), Croft et al.
patent: 5715278 (1998-02-01), Croft et al.
patent: 5898707 (1999-04-01), Takabayashi

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