Method of making a planar MOS device in polysilicon

Details Method of making a planar MOS device in polysilicon Method of making a planar MOS device in polysilicon

1985-10-02

1987-08-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 63, 437162, H01L 2176, H01L 21225

Patent

active

046883142

ABSTRACT:
A highly planarized integrated circuit structure having at least one MOS device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with at least one portion defined therein for formation of a source/gate/drain region for an MOS device. All of the contacts of the device are formed using polysilicon which fills the defined portions in the field oxide resulting in the highly planarized structure.

REFERENCES:
patent: 4259680 (1981-03-01), Lepselter et al.
patent: 4319954 (1982-03-01), White et al.
patent: 4445268 (1984-05-01), Hirao
patent: 4497683 (1985-02-01), Celler et al.
patent: 4542580 (1985-09-01), Delivorias

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