Boolean logic layout generator

Details Boolean logic layout generator Boolean logic layout generator

1986-04-07

1988-12-20

Lall, Parshotam S.

Boots, shoes, and leggings

364488, 364490, H03K 1920

Patent

active

047929090

ABSTRACT:
To reduce the size of binary decision tree-type integrated circuit representations of boolean expressions, any boolean expression or sub-expression which is fully defined by one of its partial expressions is represented by only that one partial expression. If gate branching of the decision tree is a default case which is invoked only when both partial expressions are needed to define an expression or sub-expression. These reduced size expression trees readily map into CMOS cascade logic, thereby producing low power, reasonably compact, integrated circuit representations of boolean expressions.

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Yoffa, E. and Hauge, P., "ACORN: A Local Customization Approach to DCVS Physical Design", Proceedings of the 22nd Design Automation Conf., Jun. 1985, pp. 32-38.

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