Clock generator for CMOS circuits with dynamic registers

Details Clock generator for CMOS circuits with dynamic registers Clock generator for CMOS circuits with dynamic registers

1997-11-05

2000-05-30

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By frequency

327200, 327202, 327203, 327210, H03K 906

Patent

active

06069498&

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

In digital integrated circuits for high throughput rates, the so-called pipelining principle is frequently employed in order to achieve the necessary processing speed. For this purpose, pipeline registers are inserted as buffers in the data path. These pipeline registers can be realized efficiently as dynamic holding elements (latches) distributed over the data path. A holding element of this type contains a clocked switch and a storage capacitance, the parasitic input capacitance of a respective downstream logic block being utilized as the storage capacitance. Suitable clock signals control the holding elements or the switches and hence the timing of the data flow in the data path. The holding elements operate according to the master/slave principle, the so-called master latches being activated for about half a clock period and the so-called slave latches being inhibited and, during the next half of a clock period, the slave latches being activated and the master latches being inhibited. When the latches are inhibited, the logic state at the input of the downstream logic block remains dynamically stored in the form of an electric charge on the parasitic input capacitance. The time for which this charge remains stored is restricted typically to about one millisecond on account of leakage currents. This is unimportant during normal operation, when the clock signals have a switching frequency of the order of magnitude of several megahertz.
If the clock signal is absent for some reason, for example if the generator in the system fails or starts only after a delay when the system is switched on, then either all the switches of the master latches or all the switches of the slave latches are inhibited and remain in this state. The logic state on this storage node is undefined, for example, at the latest after about 1 millisecond. These nodes are at a potential which is determined only by parasitic resistances and leakage currents. Given typical dimensioning of the transistors in the latches, the voltage at this node will be between 1 volt and 4 volts. Since the inputs of the downstream CMOS gates are not, in this case, at a defined CMOS level, of 5 and 0 volts, for example, it is possible for a parallel-path current to flow in these gates. Although the parallel-path current lies in the microampere range in a single CMOS gate, the number of undefined nodes can become very large in a circuit with a high degree of pipelining, with the result that the total current consumption may lie in the ampere range in the event of failure of the clock signal.


SUMMARY OF THE INVENTION

The object on which the invention is based consists, then, in specifying an apparatus for clock signal generation for CMOS circuits with dynamic registers in which, in the case of excessively low clock rates or in the case of the complete absence of a clock signal, the total current consumption is virtually unincreased in comparison with normal operation with an applied, specification-conforming clock signal.
In general terms the present invention is an apparatus for clock signal generation. A clock monitoring device is provided, which determines whether or not the clock rate of an input clock signal has fallen below a predetermined minimum clock rate. Devices are provided which, from an input clock signal, form a master clock signal and a slave clock signal which are in a form such that both the switches of dynamic master latches and the switches of dynamic slave lathes are closed provided that the clock rate has fallen below the minimum clock rate. Otherwise at most either the switches of the dynamic master latches or the switches of the dynamic slave latches are closed.
Advantageous developments of the present invention are as follows.
A first clock signal and a second clock signal which is the inverse of said first clock signal are formed from the input clock signal. In a first logic circuit, the first clock signal is ANDed with the inverted slave clock signal and subsequently NORed with a set signal to form the

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