Method and apparatus for selecting an optimal system bus clock i

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G06F 108

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active

060262311

ABSTRACT:
An oscillator output selector and complementary control circuitry are provided to a computer system. The oscillator output selector is used to select a series of clock pulses for usage as system bus clock. The control circuitry controls the selection being made by the oscillator output selector, in accordance to control inputs received. In one embodiment, the control circuitry receives system bus clock frequency preferences from the CPU boards as control inputs, and in response, the control circuitry causes the oscillator output selector to select the series of clock pulses having a frequency that is equal to or slower than the slowest preferred frequency. In an alternate embodiment, the control circuitry receives CPU types from the CPU boards as control inputs, and in response, the control circuitry causes the oscillator output selector to select a series of clock pulses having a frequency that will allow maximum total CPU clock frequency utilization.

REFERENCES:
patent: 5092280 (1992-03-01), Wunner et al.
patent: 5263172 (1993-11-01), Olnowich
patent: 5448715 (1995-09-01), Lelm et al.
patent: 5459855 (1995-10-01), Lelm
patent: 5491814 (1996-02-01), Yee et al.

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