Patent
1997-07-25
2000-02-15
Teska, Kevin J.
3955001, 39550006, 39550015, G06F 1750
Patent
active
060262257
ABSTRACT:
A method of laying out a semiconductor integrated circuit includes executing a schematic placement of a plurality of function cells realizing fundamental logics for a schematic routing between input/output terminals of the function cells; executing a simulation of circuit operations under virtual load conditions in consideration of a schematic length of interconnection; extracting any interconnections as critical paths from the results of the simulation; and executing detailed routing under conditions that a distance between the interconnection extracted as the critical path and an adjacent interconnection to the critical path is wider than a distance between the remaining interconnections.
REFERENCES:
patent: 5568395 (1996-10-01), Huang
patent: 5610833 (1997-03-01), Chang et al.
patent: 5638288 (1997-06-01), Deeley
patent: 5666290 (1997-09-01), Li et al.
patent: 5787268 (1998-07-01), Sugiyama et al.
Youssef et al. ("Critical path issue in VLSI design", 1989 IEEE International Conference on Computer-Aided Design, ICCAD-89, Digest of Technical Papers, pp. 520-523, Nov. 5, 1989).
Dunlop et al. ("Chip Layout Optimization Using Critical Path Weighting", Paper 9-2, ACM/IEEE 21st Design Automation Conference, Jan. 1984).
Kik Phallaka
NEC Corporation
Teska Kevin J.
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