System and method for efficiently supporting access to I/O devic

Boots – shoes – and leggings

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364DIG1, 364DIG2, 36424344, 36424345, 3642436, 3642456, G06F 1208, G06F 1300

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active

052533530

ABSTRACT:
A data processing system (10) includes a CPU (12) connected to a direct-mapped cache (14) by address bus (16) and data bus (18). The cache (14) includes a first-level cache (20) connected to a second-level cache (22) by address bus (24) and data bus (26). The second-level cache (22) of the cache (14) is connected to address bus (28) and data bus (30) by address bus (32) and data bus (34). The address and data busses (28) and (30) are connected to memory (36) and I/O device (41) by address bus (40), data bus (42), address bus (44) and data bus (46), respectively. In the system (10), I/O interface (38) decodes physical memory addresses and responds to addresses in specific ranges using first and second addresses alternately, which are chosen to collide in the data cache (14). I/O software alternates between the two addresses instead of alternating between a device register address and a reserved-region address as in prior art systems.

REFERENCES:
patent: 4802085 (1989-01-01), Levy et al.
Cousins, R., "DMA Considerations on RISC Workstations," Computer Architecture News, vol. 17, No. 5, Sep. 1989, pp. 16-23.
Tehranian, M. T., "Twin Cache Tags Enable Concurrent Micro/DMA Processing," Computer Design, vol. 24, No. 6, Jun. 1985, pp. 157-159.
Peterson, "System-Level Concerns Set Performance Gains," High Performance Systems, vol. 10, No. 9, Sep. 1989, pp. 71-77.

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