Method and apparatus for data transfer between processor element

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364DIG1, 3642601, 3642602, 3642292, G06F 1338

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active

052533468

ABSTRACT:
A method of data transfer applicable to processing elements which are interconnected by a network to form a multiprocessor system, whereby when a datum is to be transferred from a processing element to the network, the datum is sent to a transfer controller of the processing element at the same time that it is being read out from memory to be used by the processor of the processing element, or as it is being generated from the processor and written into memory. Thus, the system performance can be substantially improved, since the time required to execute each data transfer can be "hidden" within the processor execution time.

REFERENCES:
patent: 4630260 (1986-12-01), Toy et al.
patent: 5089953 (1992-02-01), Ludicky
patent: 5101478 (1992-03-01), Fu et al.
Electronic Design, vol. 33, No. 27, 1985, Hasbrouck Heights, N.J., pp. 131-137; N. Lodhi: `Assembling multiprocessor systems is a snap with off-the-shelf chips`.
Patent Abstracts of Japan, vol. 12, No. 129 (P-692)(2976) 21 Apr. 1988 and JP-A62 251 954.

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