Method and apparatus for eliminating the transpose buffer during

Details Method and apparatus for eliminating the transpose buffer during Method and apparatus for eliminating the transpose buffer during

1996-06-21

2000-02-15

Trammell, James P.

395821, 395849, 395872, 395878, 395561, H04N 100, H04N 141

Patent

active

060262176

ABSTRACT:
A method and apparatus is presented for video image compression using a unique operand decomposition technique combined with an innovative data scatter and retrieve process. This combination of features allows the use of single ported RAM structures where multiported RAMS would normally be used, such as when retrieving two operands in the same time cycle. As applied to the Discrete Cosine Transformation this method and apparatus additionally allows elimination of the usual prior art use of a separate transpose matrix buffer. The elimination of the separate transpose matrix buffer is accomplished by combining the transpose matrix intermediate results memory storage with the memory buffer used for the other intermediate results in a double buffer system. The double buffer memory locations are chosen so that the intermediate storage register address are orthogonal to the initial source addresses, thereby using one of the properties of the Discrete Cosine Transform to improve speed of operation and reduce the circuit area and system cost.

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