Transition-controlled digital encoding and signal transmission s

Details Transition-controlled digital encoding and signal transmission s Transition-controlled digital encoding and signal transmission s

1998-06-12

2000-02-15

Pham, Chi H.

Pulse or digital communications

Multilevel

Disparity reduction

370473, 714758, H04L 2534, H04J 324, H03M 1300

Patent

active

060261242

ABSTRACT:
A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including fewer than a minimum number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.
In one embodiment, an input sequence of 9-bit data blocks is balanced to produce a DC-balanced sequence of characters. A shift register generator generates a pseudo-random binary sequence. Two bits of the pseudo-random binary sequence are logically combined to determine whether to invert another bit in the pseudo-random binary sequence, thereby cycling the pseudo-random binary sequence. A bit of the pseudo-random binary sequence is used as a criterion to selectively invert all the bits in the incoming 9-bit data block, thereby producing a 9-bit data block in an output stream that, over time, tends to be DC-balanced.

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