PLL circuit having forcible pull-in function

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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327 7, 327150, 331 17, 331 14, 331DIG2, 375376, H03L 706

Patent

active

060257431

ABSTRACT:
A phase locked loop (PLL) circuit performs a frequency pull-in operation with a simple structure. The PLL circuit has an oscillating part which oscillates at a frequency corresponding to a control input signal and a phase comparing part which detects a phase difference between an oscillation output signal of said oscillator and an input frequency signal and produces an error signal responsive to a detection value. The PLL circuit further includes a forcible pull-in part which adds values of the error signal and a forcible pull-in signal, and provides a signal based on a result of addition as the control input signal. The forcible pull-in circuit includes a reference value generating circuit which supplies a reference value determining a unit change width of an oscillation signal of the oscillating part, and a computing part which computes a value of the forcible pull-in signal based on the reference value.

REFERENCES:
patent: 3873929 (1975-03-01), Willmore
patent: 4847569 (1989-07-01), Dudziak et al.
patent: 4885554 (1989-12-01), Wimmer
patent: 5307020 (1994-04-01), Marcuard
patent: 5363419 (1994-11-01), Ho

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