Process for self-aligned buried layer, field guard, and isolatio

Details Process for self-aligned buried layer, field guard, and isolatio Process for self-aligned buried layer, field guard, and isolatio

1984-09-14

1986-04-22

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29576E, 29578, 29576T, 148 15, 148175, 148DIG85, 148DIG117, 148DIG125, 148DIG128, H01L 2180, H01L 2176

Patent

active

045832820

ABSTRACT:
A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a polycrystalline semiconductor region, above a doped channel-stop region which acts as a field guard. A single mask layer determines the location and spacing of the buried portions of the isolation walls, the channel-stops, and the buried layers.

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