Testing circuit for random access memory device

Details Testing circuit for random access memory device Testing circuit for random access memory device

1987-06-25

1989-12-19

Fleming, Michael F.

Excavating

371 27, G06F 1100

Patent

active

048887722

ABSTRACT:
In a semiconductor random access memory device of the type having two or more data lines arranged in association with a single data input or output terminal is provided a memory testing circuit which is characterized in that test data is supplied to every one of the data lines and is written all at a time into a plurality of memory cells which may include those located adjacent each other, wherein the number of the memory cells into which test data is to be written simultaneously depends on the data lines to be selected so that different pieces of data can be respectively written into the individual memory cells. A portion of an address signal is used not for the selection of the memory cells during the test data write cycle of the testing operation but for controlling the inversion of the test data to be written into selected ones of the memory cells and is supplied to the memory cells associated with any one or more of the data lines, whereby pieces of data complementary to each other can be supplied to the adjacent memory cells respectively through two of the data lines, providing a basis on which an interference test can be conducted for the memory cells located adjacent each other.

REFERENCES:
patent: 4670878 (1978-06-01), Childers
patent: 4701919 (1987-10-01), Naitol
patent: 4730318 (1988-03-01), Bogholtz

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