Method for testing design timing parameters using a timing shell

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395700, 395500, 364578, 3642323, 3642643, 364265, 364DIG1, G06F 1560

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active

055176585

ABSTRACT:
A method for testing the timing parameters of a system design is presented, especially suited for use in testing for timing violations between the pins of a semiconductor device. A description of the timing constraints of the various modules of a design is written in a common non-technical vernacular, and functions as an input file. A Timing Shell Generator converts the input file description into a simulator-environment-compatible output code-language file description. The output code-language file is operative to implement the timing constraints of the original input file during simulation such that any violations of the prescribed timing constraints are indicated to the tester who can then take appropriate action.

REFERENCES:
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5095454 (1992-03-01), Huang
patent: 5105374 (1992-04-01), Yoshida
patent: 5111413 (1992-05-01), Lazansky et al.

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