Integrated-circuit power-up pulse generator circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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3072965, 3072723, 307592, 307597, 307605, 3072966, G11C 1100, H03K 301

Patent

active

048884987

ABSTRACT:
A circuit for providing a "power-up" signal pulse in response to energization of an integrated circuit logic array by a power supply. The circuit is comprised of a pulse-generating circuit and of an optional pulse-delay means. The pulse-generating circuit means detects the presence or absence of change in energization voltage potential and, in response to energization, develops an output pulse using ratioed complementary-metal-oxide-semiconductor (CMOS) logic to detect energization status during the ramp increase of the supply voltage. A feedback circuit is used to detect completion of the ramp increase and to deactivate the circuit to minimize power required for steady-state operation. The optional pulse-delay means is illustrated as narrow-width, long-channel CMOS inverters with optional capacitor loading.

REFERENCES:
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patent: 4477736 (1984-10-01), Orishi
patent: 4591745 (1986-05-01), Shen
patent: 4656369 (1987-04-01), Lou
patent: 4670668 (1987-06-01), Liu
patent: 4675557 (1987-06-01), Huntington
patent: 4692689 (1987-09-01), Takemae
patent: 4717848 (1988-01-01), Ouyang et al.

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