Reverse polysilicon CMOS fabrication

Details Reverse polysilicon CMOS fabrication Reverse polysilicon CMOS fabrication

1992-02-11

1993-10-12

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 52, 437 56, 437 57, 437 60, 257379, H01L 21336, H01L 27108

Patent

active

052525040

ABSTRACT:
A CMOS integrated circuit such as a DRAM is fabricated, in which a first layer of polysilicon is used to form transistor gates, and capacitor cell plates are formed from a second polysilicon layer.
N-wells are first formed, followed by initial oxide. The application of the CMOS process to the reverse poly technique provides enhanced alignment of critical transistor gates and permits the use of less mask steps in fabricating the CMOS circuit.

REFERENCES:
patent: 4561170 (1985-12-01), Doering et al.
patent: 4871688 (1989-10-01), Lowrey
patent: 4945066 (1990-07-01), Kang et al.
patent: 4957878 (1990-09-01), Lowrey et al.
patent: 5026657 (1991-06-01), Lee et al.

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