Boots – shoes – and leggings
Patent
1990-02-02
1992-04-07
Harkcom, Gary V.
Boots, shoes, and leggings
G06F 738
Patent
active
051034190
ABSTRACT:
A sum-of-products calculating circuit includes a bit extension circuit, wherein the most significant bit of an intermediate result of the multiplication effected by a multiplier is extended from an order one bit of the order higher than that of the most significant bit of the intermediate result of the multiplication to the sign bit of addition input data to an adder, by using the most significant bit of each of two intermediate results of the multiplication effected by a multiplier and the sign bit of each of multiplication input data to the multiplier. The data having the extended data bits are inputted to an adder as addition data for the addition performed therein. Thereby, the number of bits used for representing output data of the multiplier can be equalized with that of bits used for representing input data of the adder by a simple logic circuit without the addition of dummy bits to the addition data. Thus, the component elements of the calculating circuit is substantially reduced in number.
REFERENCES:
patent: 4121296 (1978-10-01), Snijders et al.
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4644491 (1987-02-01), Ookawa et al.
patent: 4761756 (1988-08-01), Lee et al.
patent: 4939687 (1990-07-01), Hartley et al.
Aono Kunitoshi
Araki Toshiyuki
Toyokura Masaki
Harkcom Gary V.
Matsushita Electric - Industrial Co., Ltd.
Nguyen Long T.
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